timing simulation

With the establishing of verification and test platform for SDH chip, We realize the function simulation, timing simulation and performance test of the IP soft-core.

通过建立SDH芯片验证平台和SDH芯片测试平台，实现IP软核的功能仿真、时序仿真和芯片性能测试。

The emphasis is placed on the use of VHDL logic synthesis for optimization of the multiplier. Xilinx FPGA implementation, functional and timing simulation are performed.

重点是运用VHDL逻辑综合优化该乘法器，并进行了乘法器的XILINX FPGA实现、功能仿真和时序仿真。

With research of the implementation of linear CCD drive impulse by VHDL and logical design principle, VHDL programming of drive impulse and the timing simulation of waveform are provided.

通过对超高速硬件描述语言VHDL实现线阵图像传感器CCD驱动脉冲方法及逻辑设计原理的研究，完成了驱动脉冲的VHDL程序设计和时序仿真。

And the design is proved by timing simulation.

经过时序仿真，验证了帧处理设计的正确性。

And timing simulation verified the validity of IP cores with signal delay.

时序仿真验证了IP核存在时间延时后的有效性，进一步分析验证IP核。

An FPGA based hardware scheme with performance analysis and timing simulation is presented.

然后提出了基于FPGA的系统硬件实现方案，并给出了基于该方案的性能分析、具体实现方案及时序仿真结果；

In comparison with the dynamic gate-level timing simulation, application of STA can satisfy the requirement of verification with high efficiency and performance.

实践表明，随着数字设计复杂度的增加，在后端的时序验证环节，与传统的动态门级时序仿真相比，采用STA方法的优势在于可以全面、高效地完成验证任务。

The related timing analysis and simulation results showed its effectiveness in the AUV data transmissions.

相关的时序分析和仿真结果验证了该方法在AUV数据传输中的有效性.

Function Simulation and Timing Simulation Based on FPGA Design

基于FPGA设计的功能仿真和时序仿真

Verilog HDL coding, functionality and timing simulation for all the module of the digital PLL. 4. Hardware design of the system.

编写Verilog hdl代码，并完成锁相环各个模块的功能与时序仿真。4.详细介绍系统硬件电路板设计。

The verification includes RTL simulation, gate level simulation and static timing analysis.

验证工作包括RTL级仿真 、 门级仿真和静态时序分析.

After the timing simulation, debugging on board was finished, which proved that the algorithm is realizable on hardware and indicated that the algorithm is effective and usable.

后仿真结束后通过了板级调试，证明了该算法硬件可实现性，表明了该算法的有效性和实用性。

Review of Fast Timing Simulation Techniques for Deep Submicron Integrated Circuits

深亚微米集成电路的快速时域仿真技术

Then, we carry out the timing simulation after the logic synthes and layout.

再通过逻辑综合，经过布局、布线，完成时序后仿真。

Timing Simulation of Network Delay in CMOS Standard Cell Layout Design

CMOS标准单元版图线网延迟的计算机时序模拟

The design, with Verilog HDL, realizes the IP core on FPGA after the steps of synthesis, placing, routing, functional simulation and timing simulation.

设计使用Verilog语言，对设计的十六位单片机IP进行综合、布局布线、功能仿真和时序仿真后，进行FPGA实现。

The result of the timing simulation shows that we can easily realize the data transfer and the intercommunication between PC and FPGA by using the PCI local bus controller.

仿真结果说明，采用该PCI局部总线控制器可以很方便地实现PC机和FPGA之间的数据流传输，并能很好地完成PC和FPGA间的交互通信功能。

The timing simulation and platform show the validity of the design.

通过时序仿真和硬件平台，验证了设计的正确性。

Principle simulation, module design, necessary parameters for system are accomplished by Matlab, while verification of hardware module functions, adjustment of timing between modules and obvious validation for system function are achieved by comparing the difference of simulation waves given by Max+ Plus and Matlab.

通过比较Max+Plus与Matlab的仿真结果差异来实现硬件模块的功能验证、模块之间时序关系的调整和系统功能的直观验证；

Lastly, timing simulation and performance analyzing are provided according to the actual application. The simulation results prove the design is right and has high performance.

最后，结合地面网关的具体应用，给出了相关的时序仿真与性能分析，时序仿真和验证结果表明论文中所给出的设计方案能够正确完成地面网关的AAL5适配功能，性能良好，达到预期目标。

The functional verification of this design includes functional simulation, timing simulation, board-level debugging, and system testing.

验证流程是功能仿真、时序仿真、板级调试，最终通过系统测试，验证了该设计的功能。

At last it shows the results of synthesis and timing simulation diagram.

最后给出了相应的综合结果和时序仿真图。

Timing simulation of circuit being processed on the MAX+ PLUS ⅱ and testing the download.

用MAX+PLUSⅡ软件进行了电路时序仿真分析，并进行了下载测试。

The result of waveform timing simulation is consistent with what we want to get.

并经过波形仿真，所得到的结果与预先设计的要求达到一致。

Finally, the detail of each module with testing data results and the timing simulation waveform is explained.

其次给出了测试平台的搭建、实现结果及时序仿真波形图。

On this basis, the article gives the design and timing simulation of main function modules.

在此基础上，文章给出了主要功能模块的具体设计和时序仿真结果。

Finally, by analyzing the results of timing simulation, it validates the practicality of synchronous circuit.

最后通过对位、帧同步电路的时序仿真结果分析，验证了同步电路的实用性。

Switch-Level Timing Simulation Using RC Network as Delay Model

用RC网络作延迟模型的开关级定时模拟

Comparing the results of BRT active priority and fixed timing simulation, it is effective to reduce BRT delay by active priority strategies application.

通过对比主动优先和固定配时的仿真结果表明，BRT主动优先能有效地减少BRT延误。

Finally, the top-level connection diagram of all modules has been shown and passed the timing simulation.

最后给出所有模块的顶层连接图，并通过了整体的时序仿真验证。